This invention relates broadly to the field of charge coupled devices, and more particularly, to a structure having double electrode conductive layers of doped polycrystalline material, the electrode layers being aligned to eliminate substantially overlapping of one conductive layer to another.
One of the most difficult process steps in fabricating charge coupled devices is to ensure that the gate electrodes on different conductive levels overlap one another as shown in FIG. 1. The reason for this is that, in general, conventional fabricating techniques cannot guarantee perfect alignment of the gate electrodes from one layer to another. It is understood that gaps laterally registered between the first and second electrode layers generally cause corresponding discontinuities in the surface potential within the charge transfer channel of the charge coupled device resulting in inefficiency of charge transfer therethrough. While the overlapping of electrodes between layers eliminates this problem, it causes an increase in capacitance between electrode layers, more commonly referred to as overlap capacitance. As a consequence, a charge coupled device gate clock driver has additional capacitance to drive which, in some cases, may be large compared to the active capacitance of the gate channel. For some special charge coupled device structures, like those having non-destructive readout capabilities, for example, the amount of charge contained in each well is measured with a certain degree of accuracy. Devices of this type may employ a split electrode or a floating clock electrode structure for the sensing electrodes in which it is most desirable to eliminate substantially all parasitic capacitance, including particularly the overlap capacitance. In these devices, the sensitivity of detecting charge goes down with the amount of parasitic capacitance associated with each gate or sensing electrode.
Attempts have been made in the past to align the double layer electrodes to eliminate this overlap capacitance. One such proposed structure is disclosed in a U.S. Patent bearing U.S. Pat. No. 3,967,365, issued on July 6, 1976 by Hans Friedrich and entitled "Process for the Production of a Two-Phase Charge Shift Assembly". The proposed device of Friedrich is described as being constructed by applying an insulating layer to a semiconductor substrate, applying a highly resistive polycrystalline silicon layer to the insulating layer, forming metal electrodes on the polycrystalline layer to thereby protect the zones lying beneath the electrodes, implanting charge carriers by ion implantation in an oblique direction into the zones of the layer of polycrystalline silicon to thereby form conductive electrodes in the layer which serve as electrodes between the electrically insulating zones of polycrystalline material.
While the proposed Friedrich structure does eliminate many processing steps and has the additional advantage of providing contact between the double electrode layers during the processing operation, it should be noted that, without special care in fabrication, metal electrodes should be used for the second layer. If polycrystalline silicon were used for the second electrode layer, during the implanting of charge carriers in the ion implantation step, any dopant implanted in the polysilicon second layer may, under certain conditions, go through the electrode at that layer and into the underlying area possibly diffusing therethrough in all directions. In this case, the insulating gap between the conductive electrodes may not be reliably guaranteed for all the gate electrodes in the channel.
An undesirable feature in using metal for the second layer electrode is that, with conventional processing techniques, it is very difficult to fabricate very narrow width gate electrodes and spacings therebetween. The main reason is that metal electrodes such as aluminum, for example, undercuts during most chemical etching processes. Consequently, special techniques, such as ion milling, for example, have been used at times to remove the aluminum to form the necessary narrow channels between the gate electrodes. Of course, it is understood that with the use of polycrystalline silicon as the second layer very narrow gate widths and spacings therebetween may be easily accomplished with conventional fabrication techniques.
A further disadvantage with using metal for the conductive electrodes of the second layer is that during the annealing process which is usually required in the fabrication of charge coupled device semiconductors particularly to make ohmic contact with the N.sup.+ and P.sup.+ diffusions, the phenomenon of metal spiking may occur. In this phenomenon, during the annealing process, very thin icicle-like pieces of metal may grow from the second layer metal electrode and may extend through the undoped polysilicon regions to the adjacent doped polysilicon electrodes causing possibly an electrical short between electrodes to occur during operation.
Moreover, even if it is assumed that metal gate electrode structure may be satisfactory used for some charge coupled device applications, it still remains that the ion implantation step in producing the proposed Friedrich structure may not be reliable enough to ensure an insulating gap between all gate electrodes in the charge coupled device channel. For this reason, a low production yield may exist whereby the per unit production associated costs may be excessive.
From the above, it appears that in dealing with charge coupled device structures having electrodes on different conductive levels, a polycrystalline material, such as polycrystalline silicon, for example, may be more suitable than metal for achieving narrow electrode widths and spaces therebetween using conventional processing techniques. When overlapping of electrodes is necessary using polycrystalline silicon or the like, there remains the problem of repeatably establishing small amounts of polysilicon undercut during etching process. To eliminate this electrode overlap necessity, the gate electrodes would have to be aligned with respect to one another to ensure that discontinuities in surface potentials in the charge transfer direction would be substantially eliminated. While the proposed Friedrich structure (U.S. Pat. No. 3,967,365) appears to achieve such a device, a number of disadvantages associated therewith have been uncovered. The present invention as disclosed below provides for a device which overcomes most of the uncovered undesirable features of the proposed Friedrich structure. Applicant's structure is believed to provide for a high production yield device by ensuring a high degree of reproducibility in achieving alignment of the double layer gate electrodes and insulation between the gate electrodes in the device channel. Another advantage of Applicant's structure is that the double layer electrode alignment permits smaller average gate widths since the tolerances for electrode overlap may be substantially eliminated.